Chip Design And Verification

FPGA and Asic verification

• RTL/Gate Simulation
• Languages - Verilog, VHDL, SystemVerilog, C/C++, SystemC and e Methodologies - OVM, UVM, eRM and SystemC Design and Implement Methodologies.
• SVA/PSL Assertons
• Analog Mixed Signal Verificaiton

RTL Design

• RTL Coding
• Micro-Architecture
• Microprocessors
• IP Acquistion and Integration
• SVA/PSL Assertions
• Mixed Signal System Design

Functional Verification Managment.

• Coverage Driven Verification
• Assertion Based Verification
• Verification and Test Plans
• Coverage Models
• Coverage Analysis and Closure

Traning

• System Verilog
• OVM/UVM
• Verilog
• VHDL
• SVA and PSL